SUMMATION OF BINARY CODES WITHOUT CARRY

These two numbers fully determine the range of numbers that can be presented by a binary code (2). For example, for an 8-digit binary without a signed integer, the range of numbers is 0...255. For a 16-bit code, the range equals 0...65535. The examples of binary codes are the code of Gray, Baudot code, Hamming code, ASCII, etc. 35. Kondratenko, N. R. Application of Type-2 Membership Functions in Fuzzy Logic Systems [Text] / N. R. Kondratenko // Research Bulletin of the National Technical University of Ukraine “Kyiv Politechnic Institute”. – 2016. – Vol. 2. – P. 43–50. doi: 10.20535/1810-0546.2016.2.51636 36. Karnіk, N. Type-2 Fuzzy Logіc Systems [Text] / N. Karnіk, J. Mendel, Q. Lіang // IEEE Transactions on Fuzzy Systems. – 1999. – Vol. 7, Issue 6. – P. 643–658. doi: 10.1109/91.811231 37. Kondratenko, N. R. Evolyucijnyj poshuk informatyvnykh oznak iz zaluchennyam eksperta v zadachi ocinky yakosti arteziansjkoi vody [Text] / N. R. Kondratenko, O. O. Snihur // Visnyk Vinnycjkogho politekhnichnogho instytutu. – 2015. – Vol. 3. – P. 96–101. 38. Teoriya informatsii i ee prilozheniya (sbornik perevodov) [Text] / A. A. Harkevich (Ed.). – Мoscow: Fizmatgiz, 1959. – 328 p.


Introduction
Binary code is a general designation of the code, by which messages can be transmitted in sequences that have two characters (for example, "0" and "1").In general, the number of combinations (codes) of n-digit binary code is equal to the number of locations with repetition of n elements by m m P(n,m) n . = For a binary code, the number of combinations equals: where n is the digit capacity of a binary code.
The minimum possible number that can be written down by such a binary code equals 0. The maximum possible number that can be written down by such a binary code is determined by the formula n M 2 1.
= − These two numbers fully determine the range of numbers that can be presented by a binary code (2).For example, for an 8-digit binary without a signed integer, the range of numbers is 0…255.For a 16-bit code, the range equals 0…65535.
The examples of binary codes are the code of Gray, Baudot code, Hamming code, ASCII, etc.
The carry of one to a higher level in the basis of Rademacher leads to the decrease in fast performance of identifying correct signals at the outputs Si of the one-digit adders.The magnitude of this decline is proportional to the digit capacity of numbers and time delay of the signals in typical logical elements.The maximum time of the operation of summation occurs when the carry, which appeared in the first bit, passes through all the other bits (for example, when compiling codes 11...11 and 00…01).Modern achievements in the creation of high-performance processors are based on the designs of the theory of parallel computing.
The method of parallel computing in the Rademacher TNB, in particular, is based on the recurrent binary codes.Extension of the apparatus of obtaining these codes is one of the most central and practically important problems in this theory.The [2,3] demonstrated, accordingly, receiving recurrent binary code using cyclic shift of the original 4-digit non-zero code fragment -1111 and the original zero code fragment of 0000.Since the specified original code fragments are part of a complete combinatorial system with repetition (Table 1), the research is actual into the process of formation of recurrent binary codes with the help of the rest of the initial code fragments in Table 1, which allows extending the apparatus of obtaining recurrent binary codes, controlling the selection of a code at the stage of designing a computing device and the classification generalization of the binary codes with the aim of simplifying the structure of the subject area, increasing the diversity of the systems of binary codes, in particular, for arithmetic operations with binary numbers.
The relevance of the classification generalization of the binary codes for arithmetic operations is also in presenting the data of the systems of binary codes by a unified general table of the data, and, therefore, the unified general hardware costs at the level of an electronic device.

Literature review and problem statement
The [4] considered the design of the adder of binary numbers with a choice of carry (Carry Select Adder), which is one of the fast-performing versions of the parallel adder.The feature of the Carry Select Adder is in that the adder has linear complexity of the algorithm of the calculation, however, within the range of 16-128 bit scheme, it shows better efficiency of calculation compared with the scheme of the adder with logarithmic complexity of the calculation.The disadvantage of the Carry Select Adder is the organization of technology of selecting the carry through the split of the structure of the adder into separate groups of logical elements, each of which contributes to the delay of the carry signal (more groups -larger delay), which with increasing the digit capacity of the scheme reduces the productivity of computing.
The [5] demonstrated better efficiency of multiplying binary numbers for a 64-digit sign multiplier using the technology of Carry Select Adder (CSA), compared with the Carry Look-Ahead Adder (CLA).Thus, the results of the paper [5] confirm the specifics of the Carry Select Adder that were examined in the analysis of the work [4].With the increase in the digit capacity of a sign multiplier, more promising is the technology of the CLA, since the latter uses a cascading scheme [6].The calculations organized by a cascade scheme in the CLA demonstrate a significant advantage exactly while increasing the bit capacity of a device's scheme.
The [7] examined designing the adder of binary numbers with a skip in the carry (Carry Skip Adder), which is a modification of the parallel adder with the structure of lower hardware costs and energy consumption compared to Carry Look-ahead Adder.The feature of the Carry Skip Adder is in that the adder occupies a technological niche between the Ripple Carry Adder with greater productivity of computing and Carry Look-ahead Adder with lower hardware costs.The disadvantage of the Carry Skip Adder is the organization of the technology of skipping the carry through the breakdown of the structure of the adder into separate groups of logical elements, the half of which contributes to the delay of the transfer signal, which limits the productivity of computing, that is why the Carry Skip Adder technology achieves the complexity of the algorithm of calculation not less than linear.
The [8] demonstrated better performance in multiplying binary numbers for a 32-bit multiplier using the technology of Carry Save Adder (CSA) compared with Carry Look-Ahead Adder (CLA).The feature of using the CSA for the process of the multiplication by a multiplier is in the way of performing of addition of partial multiplications (Carry Save) and their final summation.The technology of Ripple Carry Adder is used only at the final stage.The multiplier with the CSA requires fewer complete adders than the multiplier with the CLA.Since the Carry Look-Ahead Adder uses a cascading scheme [6], then with increasing the digit capacity of binary numbers, the CLA becomes more promising.However, the analysis in [8] is limited by the consideration of calculations of 32-digit numbers while other data are not presented.
The [9] presents designing and implementation of an 8-bit Carry Look-ahead Adder with low power consumption based on the 180 nm CMOS technology.The peculiarity of the CLA is the lowest depth of the adder's scheme; in particular, for a 2048-bit scheme of the CLA, the depth is 26 logical elements.An adder has logarithmic complexity of the calculation algorithm.Therefore, the CLA is the main functional unit in arithmetic-logical devices due to its high performance speed.However, the lower depth of the adder's scheme is achieved by increasing the complexity of the scheme, which is a disadvantage of a Carry Look-ahead Adder.That is why 8-bit CLA is sufficient.In the practical context, 32-bit [8] and 64-bit CLA [5] are known.
The [10] presented a scheme of a serial adder with reverse logic gates.Reverse logic is able to effectively dissipate heat energy, which is the main requirement when designing VLSI with low power consumption.Reverse serial adder [10] is based on the serial adder of binary numbers which includes a complete single-digit adder and a trigger.The disadvantage of the latter adder is that it implements the technology of Ripple Carry Adder in the worst version, since the chain of carry consists of three logical elements, and, therefore, when adding n-bit numbers, the chain of carry will consist of 3n logical elements.Speeding up calculations is possible when using a serial adder without carry.In this case, a complete single-digit adder and a trigger will be replaced by one logical element -OR or AND, which is the advantage of the reviewed technology.
The [11] presents designing and implementation of a 16-bit Ripple Carry Adder (RCA) with low power consump-tion based on the 45 nm CMOS technology.The peculiarity of the RCA is the least complexity of the scheme in the class of parallel adders that provides the scheme's performance with minimal consumption of power and thus it becomes possible, to certain extent, to solve primary problems in today's VLSI that arise due to two main reasons.One is the continued work of a battery for servicing mobile and portable devices, and the second is due to the increase in the number of transistors on a single-chip VLSI.The disadvantage of the RCA is the increase in the carry signal chain, which slows down the establishment of stable values of the signals at the Si outlets of the RCA one-digit adders.
The operation of summation of binary numbers in the digital technologies [4,5,[7][8][9][10], with the exception of [11], implies a way to reduce the carry.Summation in a positional system without carry was first demonstrated using the Galois field codes that are obtained by using theoretical-numerical transformations over the Galois field and the initial non-zero code fragment.
However, the codes for the operation of summation without carry in a positional system can be obtained through the initial, zero and each of non-zero blocks of complete combinatorial system with repetition (Table 1).Generated codes for the operation of summation are categorized only as binary and in this case they have recurrent properties.
Assume P(2, n) is the class of combinatorial systems with initial blocks of complete combinatorial system with repetition (Table 1).Then P(2, 1111) -an instance of the class P(2, n) is a combinatorial system with a 4-bit initial block -1111.P(2, 0000) -an instance of the class P(2, n) is a combinatorial system with a 4-bit initial block -0000.P(2, b i ) -an instance of the class P(2, n) is a combinatorial system with a 4-bit initial block -b i Table 1.
Unlike [2,3], in this paper the Galois field codes, codes XAND are determined by the respective instances P(2, b i ) of the class P(2, n) by way of their selection on the ring structure using the original block b i Table 1.This means that the principle of the construction of the system of binary codes by its code-beginning (block-beginning) is located within the range of the complete combinatorial system with repetition (Table 1).Therefore, all the blocks in Table 1 are equal in the principle of the synthesis of the corresponding system of binary codes P(2, b i ).In its turn, the chosen system of binary codes (an instance of P(2, b i ) in the class P(2, n)) is equal in its use, among other systems, for example, in arithmetic operations.
Since the use of binary codes for the operation of summation without carry is the task still unsolved, this paper demonstrates a new standard of the synthesis of binary codes, which comes down to that the set system of binary codes (instance of P(2, b i ) of the class P(2, n)) is selected on the ring structure with the help of corresponding initial block of complete combinatorial system with repetition.Similarly selected are the other systems of binary codes, with their blocks-beginnings, that can be applied to carry out the operation of summation without carry, thus expanding the apparatus of the synthesis of recurrent binary codes for their use in digital technologies.

The purpose and objectives of the study
The aim of this work is to construct a scheme of a parallel adder of binary codes without inter-digit carries and to determine the quality indicators of such an adder.
To achieve the set goal, the following tasks are to be solved: -to determine the properties of recursive method of the synthesis of binary codes; -to establish the validity of the use of any block-beginning of complete combinatorial system with repetition (Table 1) for the synthesis of recurrent binary codes P(2, b i ); -to obtain an estimate of the complexity of the algorithm of calculation of signals of the sum of a parallel adder of binary codes without carry; -to compile a protocol of computing of the operation of summation of binary codes without carry, to conduct the test of the synthesized adder to match the results of the operations of summation of binary numbers and the compiled protocol and to specify the range of adding the numbers of the adder of binary codes without carry; -to perform a comparative performance analysis of the calculations of signals of the sum in the scheme of a parallel adder of binary codes without carry to the scheme of a parallel adder with a parallel way of the CLA carry (Carry Look-ahead Adder).

Recursive method of synthesis of binary codes
The method of recursion provides for a synthesis of binary codes with the necessary properties for the operation of summation without carry.
1. Recursion submits the next code (or a recurrent sequence element) by using logical operation on the previous code (element).Thus all n-digit codes are the result of a cyclic shift of the original code fragment with the key (for the case of a 4-digit code).2. Compiled in this way, the system of codes must possess the properties of a ring, which gives, in particular, the formation of the initial code of the system at the operation of the shift in the last code by one bit of a recurrent sequence.
3. The set of binary codes of any instance P(2, b i ) in the class P(2, n) with the properties of a ring relative to the operation of summation is the additive group of the instance P(2, b i ) with a ring structure that can be marked as -P(2, b i ) + .4. The system of codes will have a ring structure only when it contains one of the two combinations of binary numbers: 0000 or 1111 (for the case of 4-digit binary numbers).
5. It follows from the property 4 that, based on complete combinatorial system with repetition (Table 1), the formation of two ring structures, one of which contains the code 0000 (4), is possible and the other one contains the code 1111 ( 5) 6.In the system of codes with a ring structure, made by using the XOR operation, the code 0000 is missing, in the system of codes with a ring structure, formed by using the XAND operations, the code 1111 is missing (for the case of 4-bit binary codes).
7. The order of alternation of recurrent binary codes in a ring structure is the same for all systems of binary codes (for all instances P(2, b i ) in the class P(2, n)).For example, for a ring structure (4), the order of alternation of codes is as follows: where n is the digit capacity of a binary code.9.It follows from the property 8 that the range of numbers that can be presented by the binary recurrent codes (6) consists of where n is the digit capacity of a binary code.
For example, for an 8-bit binary without a sign integer, the range of numbers, which can be presented by binary recurrent codes is 0…254.For a 16-bit, without a sign code, the range equals 0…65534.

Recurrent binary codes
For binary, such as 4-bit codes, at logical operation XOR, each of 2 n -1 n-digit non-zero code combination of recurrent sequence is the result of cyclic shift of any initial non-zero code fragment that belongs in complete combinatorial system with repetition (Table 1) with the key Compiled in this way, the system of codes has a ring structure, which provides, in particular, for the formation of initial system code at the operation of the shift in the last code of the system by one bit of recurrent sequence.
Table 2 presents all 4-bit initial code fragments of complete combinatorial system with repetition (Table 1), with the exception of zero (0000) and corresponding recurrent sequences of the code elements, formed by the key Logical operation XAND allows obtaining recurrent binary codes by a cyclic shift, starting at zero (0000) initial fragment [3].
All sequences (Table 2) present 4-bit binary recurrent codes shifted by one bit by to each other, the values of which are given in Tables 3, 4.   For any given initial code fragment (Table 2), for example, x 1 , x 2 , x 3 , x 4 with the key all other representations of the bits of corresponding recurrent sequence (Table 2) can be obtained through the initial: x From the review of dependencies (7) we see that in the calculations of each bit of the recurrent sequence, starting with x 5 , the first four bits participate.

Arithmetic operation of adding binary codes without carry
The operation of summation of binary codes А(х) and D(x) is the recursive shift in the selected sequence (Table 2), starting from the initial position of the code А(х) on a number of discrete positions defined by the decimal equivalent of the code D(x).Thus, the implementation of the indicated operation of summation boils down to simultaneous parallel mutually independent formation of each bit of the result of the calculation as the sum of the operation ⊕ without having to perform the operations of inter bit carries.The calculation of each result of the operation is carried out in one cycle.The process of calculation is invariant to the digit capacity of a word of data.
To perform the operation of summation, the codes-summands are presented by using dependencies (7).
During the operation of summation, the code А(х) (Table 5, a) is exposed to the actions defined by the dependencies of the code D(x) in the recurrent sequence (Table 2), which correspond to the value of the code D(x) (Table 5, b).The dependencies of the code D(x) set a certain programming procedure (vector) over the code А(х) for the calculation of each digit of the sum C(х) (Table 5, c).
The dependencies (7) of the code of the number А(х) -0101 (4 10 ) of the example 1 are in the 4th line of Table 8, the vector D'(x) is in the 6th line of Table 8 (Table 6).

Table 5
Expressions for the 4-bit codes: a -А(х), b -D(x), c -C(х), presented by dependencies ( 7) А(х) -0101 (4 10 ) D(x) -0110 (6 10 ) C(х) -0100 (10 10 ) According to the program D'(x) (the 6th line of Table 8), for the calculation of the first digit of the sum C(х), all four dependencies of the code А(х) (Table 5) must participate.To calculate the sum C(х) in the second digit, the first three dependencies of the code А(х) (Table 5) must participate.To calculate the sum C(х) in the third digit, the dependencies of the second, third and fourth bits of the code А(х) (Table 5) must participate.To calculate the sum C(х) in the fourth digit, the dependencies of the first and the third bits of the code А(х) (Table 5) must participate.
The program procedure D'(x) over a 4-bit code А(х) can be presented by a table (Table 7).In the first line of Table 7, the dependencies of the code А(х) (Table 5) are recorded to calculate the first digit of the sum C(х) in accordance with program procedure D'(x) (Table 8).In the second line of Table 7, the dependencies of the code А(х) (Table 5) are recorded to calculate the second digit of the sum C(х) in accordance with the program procedure D'(x) (Table 8) and so on.Indexes at x in the far left column of Table 7 must be replaced with the corresponding indices for the sum C(х)x 11 =x 2 ⊕x 4 , x 12 =x 1 ⊕x 3 ⊕x 4 , x 13 =x 1 ⊕x 2 , x 14 = x 2 ⊕x 3 .Dependencies of the code of the number А(х) and the vector D'(x) of the example 1 in algebraic representation of Table 8 Calculations over the 4-bit code А(х), which are defined by the program procedure D'(x)

1. Two general tables of representation of binary codes
x x ⊕ P(2, b i ) of the class P(2, n) allows, to all possible options of summation of binary codes, presenting the data about the vector of the code D(x) by two general tables (Table 8, 9).

1. 1. General table of binary codes in algebraic representation
Table 8 displays the data on the vector of the code D(x) in algebraic representation by dependencies (7).Table 8 is a general table of representation of codes for all combinatorial systems P(2, b i ).
For the code D(х) -1111, for example, at the operation of summation with any code А(х), the program procedure (vector) D'(x) over the code А(х) in algebraic representation will take the form:

1. 2. General table of binary codes in bitmap representation
Table 9 displays the data on the vector of the code D(x) by the dependencies (7) using the numeric symbols (bits).Table 9 is a general table of representation of codes for all combinatorial systems P(2, b i ), where the presence of a character in the dependencies ( 7) is indicated by one, and the absence of a character is indicated by zero.
For the code D(х) -1111, for example, during the operation of summation with any code А(х), the program procedure (vector) D'(x) over the code А(х) in the bitmap representation will take the form: 1 st bit 2 nd bit 3 rd bit 4 th bit D'(x)=> 1 1 1 1 In a shortened record of the vector D'(x), the sign of the operation is omitted, for example: -D(х) D'(x) 14 0111 0011 1000 0100 0010 In the end Table 9 will take a compact view.

2. Adding binary codes in bitmap representation without carry
Since arithmetic operations in electronic schemes are carried out by using physical signals, which, in turn, are defined by substitution, in accordance with the bits of binary codes we will present binary codes of the numbers А(х), D(x), C(х) in bits, where the presence of a character of the sequence ( 7) is denoted by one, while the absence of a character is denoted by zero.For example, the 4-bit code 1 4 x x ⊕ for any initial code fragment of combinatorial systems P(2, b i ), in the bitmap representation will look like 1 0 0 1, ⊕ ⊕ ⊕ the 4-bit code 1 2 3 4 x x x x ⊕ ⊕ ⊕ in the bitmap representation will take the form 1 1 1 1.
⊕ ⊕ ⊕ Example 2. For the initial code fragment 1111 (as for other initial code fragments), the vector D'(x) and the code А(х) from the example 1 can be presented in bits (Table 11).
The program procedure D'(x) over the code А(х) from the example 1 (Table 5) will look like (Table 10).
Dependencies (7) are used to construct the vector D'(x), so in general one can consider missing the character of the vector D'(x), which is denoted by 0 D .The vector D'(x) with regard to the missing characters will look like (Table 12).

Table 12
Vector D'(x) (the 6th line of Table 8) with regard to the missing characters The calculations in Table 11 will be written down by equations ( 8), each of which is formed by substituting the bits of the code А(х) in the structure of the corresponding digit of the vector D'(x), given the missing character 0 D .For another option of adding codes it is necessary to perform another substitution of the А(х) code bits in the structure of the corresponding digit of the vector D'(x) and to repeat the considered order of arithmetic operation.
The obtained values of the equations x 7 =0, x 8 =1, x 9 =0, x 10 =0 correspond to the bits of the code of the sum C(х).Indices at x must be replaced with the corresponding indices for the sum C(х) -x 11 =0, x 12 =1, x 13 =0,x 14 =0.
Substitution at the level of the scheme requires a process of logical operation, which for the missing characters of the vector D'(x) gives the following options matching the wildcard characters: The last option of the substitution inverts one into zero (excludes the bit-unit of the code A from logical process), which requires a logical element I for the scheme.Substitution with the present characters of the vector D'(x) gives other variants of the logical substitution of the variables: that is, zero becomes zero, one becomes one.
The process of the substitution with the specified logic is represented by the equations ( 9), in which the A code is written down by the initial values of the bits -0101 (4 10 ): The obtained values of the equations x7=1, x8=0, x9=1, x10=1 correspond to the bits of the code of the sum C(х).Indices at x must be replaced with the corresponding indices for the sum C(х) -x 11 =1, x 12 =0, x 13 =1, x 14 =1.

3. Scheme of the adder of binary codes without carry
By the equations ( 9) a combination scheme of the 4-bit adder of binary codes is synthesized.For the first digit of the code of the sum C(х) x 11 such a scheme, which is built based on the adder of the Galois field codes [12] is presented in Fig. 1.Similarly to the scheme in Fig. 1, the schemes of other digits of the adder of binary codes are built, for the synthesis of which the appropriate logical equations are used similar to (9).Fig. 2 presents the scheme of the first digit of the 8-bit adder of binary codes without carry on the logical elements AND and XOR.
Fig. 3 presents the scheme of the first digit of the 16-bit adder of binary codes without carry on the logical elements OR and XAND [3].
Table 13 Calculations defined by the program procedure D'(x) (the 6th line of Table 9) over the 4-bit code А(х) -1111 (4 10 ) of the initial code fragment 1000 represented in bits The obtained values of bits in the lines of Table 13 x 7 =0, x 8 =1, x 9 =1, x 10 =0 correspond to the digits of the code of the sum C(х).Indices at x must be replaced with the corresponding indices for the sum C(х) -x 11 =0, x 12 =1, x 13 =1, x 14 =0.

Table 14
Vector D'(x) (7th line of Table 9) with regard to the missing characters Table 15 Calculations defined by the program procedure D'(x) (7th line of Table 8) over the 4-bit code А(х) -1100 (2 10 ) of the initial code fragment 1011, presented in bits The obtained values of the digits in the rlines of Table 15 x 8 =0, x 9 =1, x 10 =1, x 11 =1 correspond to the digits of the code of the sum C(х).Indices at x must be replaced with the corresponding indices for the sum C(х) -x 10 =0, x 11 =1, x 12 =1, x 13 =1.

The structure of functional connection of the control output of a decoder with a string of intermediate coefficients d ji of the logical vector D'(x) in the scheme of the adder of binary codes
The calculation of the 4-bit code of the sum C(х) requires submitting to one of the input of the adder 16 (2 k , where k is the digit capacity of the adder) of the bits of intermediate coefficients d ji of the logical vector D'(x).For this, one needs a functional connection of the control output of the decoder with a string of intermediate coefficients d ji of the vector D'(x) belonging to the code D(x).One of the devices that can provide such a functional connection is a memory device.Another solution might be a multiplexer, which, however, gives a linear total complexity of computing in the adder's scheme.
Functional connection of the adder with a string of intermediate coefficients d ji of the logical vector D'(x) uses the decryption of the k-digit code D(x) into a 2 k -digit unitary code, in which one determines current vector D'(x) in the line of Table 9.
For the operation of summation of binary codes, controlling output of the decoder (one in unitary code) connects with the corresponding line in Table 9, after which all 2 k bits of the line are submitted onto 2 k inputs d 11 , d 12 , d 13 , d 14 … d 41 , d 42 , d 43 , d 44 of the adder (Fig. 4).
The structure of the functional connection of the adder with a string of intermediate coefficients d ji of the logical vector D'(x) consists of the circuit of a memory device, a decoder and the scheme of the adder of binary codes of 4 digits.To the inputs d 1 , d 2 , d 3 , d 4 of the structure, the bits of the code D(x) are submitted; to the inputs a 1 , a 2 , a 3 , a 4 the bits of the code А(х) are submitted.The bits of the code of the sum C(х) receive the adder S 1 , S 2 , S 3 ,S 4 at the outputs.
With increasing digit capacity of an adder, the principle of constructing the structure of the functional connection of the control output of the decoder with a string of intermediate coefficients d ji of the logical vector D'(x) does not change.

Computation protocol of the 4-bit adder of binary codes
The range of adding numbers of an adder of binary codes without carry is: where n is the digit capacity of a number.A number of options to add a multi digit parallel adder of binary codes without carry is: where n is the digit capacity of a number.
Having computed the values b, we determine the number of strings of the computation protocol of the 4-bit parallel adder of binary codes without carry, which is 120 lines (Table 16).
The logic of the work of the adder of binary codes (Fig. 4) corresponds to the computation protocol of the adder for the initial code fragment -1111 (Table 16).For other initial code fragments, the codes in the computation protocol will have different location, corresponding to the initial block of the chosen system of binary codes.

The complexity of the algorithm of calculation of the adder of binary codes without carry
The schemes in Fig. 2, 3 represent a structure that implements multi operand summation [13,14], when at the same time the neighboring pairs of terms are added, and then their sums (Table 17).
Table 17 The algorithm for pairing (n=2 If n=2 k , where n is the number of terms, then the algorithm for pairing consists of k steps (cycles): the first step includes n/2 addition, the second -n/4, ..., the last -one addition.The number of steps k is determined by the formula: This variant of multi operand addition is implemented by a cascade scheme ("pyramid") [13][14][15][16], and it has logarithmic complexity.
Assume as one computing step the calculation on one logical element, in the serial connection of the elements of the scheme.Given the fact that the logical XOR elements in the scheme in Fig. 2, 3 are connected by a cascade scheme, the complexity of the algorithm of calculation of signals of the sum will look like O(log 2 n+1), (11) where n is the digit capacity of binary codes, which equals the number of terms in the cascade scheme of the summation.In the (11), log 2 n reflects a cascade connection of XOR logic elements; one displays the logical item I, included sequentially.
The adder of binary codes (Fig. 4) includes a decoder, a memory device and the circuit of summing of the coefficients d ji with bits of the code of the number A.
The connection of multi-pass logic elements AND (Fig. 5) of the decoder can also be organized according to the cascade scheme.

Fig. 5. Multi-pass logic element AND
Then the complexity of calculating of the decoder can be presented by the estimation (11), in which one reflects the Invertor, connected in series (Fig. 4).The estimation of the total complexity of calculation by logical elements XOR and the decoder will look like O(log 2 n+1+log 2 n+1)=O(2log 2 n+2). ( For quick selection of bits of intermediate coefficients d ji of the logical vector D'(x) from the string in Table 9, one requires a device of constant memory, the cells of which will store the values of the bits of the logical vector D'(x) after their recording.These requirements are met by, for example, static memory.Fig. 6 presents a cell of static memory, in which the key of the cell is modeled by a trigger.

Fig. 6. Cell of static memory
We see in Fig. 6 that the unit of the unitary code of a decoder chooses recorded bit of the vector D'(x) (Table 9) by using the chain of the depth in eight (including Invertor on the elements AND) logical elements, connected in series.This number of logical elements does not depend on the digit capacity of the adder of binary numbers.That is why the estimation (12) will increase by 8 elements more, connected in series and, therefore, will manifest the overall complexity of the algorithm of calculation in the parallel adder of binary codes without carry.O(2log 2 n+10)=O(log n). ( The estimation (13) specifies the logarithmic growth of the complexity of the algorithm of the calculation -doubling the digit capacity of the adder n increases the time of determining correct signals of the sum by a stable value.

Comparison of the structures of parallel adder without inter digit carry and parallel adder with a parallel way of carry
Table 18 presents the dynamics of increasing the depth of the scheme of parallel adder with a parallel way of carry CLA (Carry Look-ahead Adder), the synthesis of which is based on the model of calculation of the adder in the form of oriented acyclic graph that represents a binary tree [6].Since the acyclic graph provides a cascading scheme, then, therefore, the number of computational steps of the graph optimizes (indicates the minimum sufficient) number of carries for the operation of addition of multi digit binary numbers in the scheme of the parallel adder with a parallel way of carry CLA.The estimation of the complexity of computing in the scheme of the adder with increasing dynamics of the depth of the scheme of the adder in Table 15, with increasing the digit capacity of the adder looks like O(2log 2 n+4).( 14) Fig. 7 presents the dynamics of increasing the depth of the scheme of the parallel adder without inter digit carry (AWC) and the parallel adder with a parallel way of carry CLA.
Given the Fig. 7, we see that the complexity of the algorithm of the calculation of both adders obeys the logarithmic law.

Discussion of the results of the study of the operation of summation without inter digit carry for binary codes
The studies of this work demonstrate that: 1.The codes known in the literature for the operation of summation -for example, Galois field codes [2,4], XAND codes [3], are determined by the combinatorial systems with initial blocks of complete combinatorial system with repetition P(2, n) (Table 1).In its turn, the combinatorial systems (instances P(2, b i ) of the class P(2, n)) are the systems of binary codes and therefore belong in the same object.Thus, the only basis of the specified binary codes indicates the usefulness of their classification generalization, within the range of operation of summation, on the basis of a single criterion -an object of binary codes.And appropriateness here is the necessity, so the usefulness of this study lies in the fact that they predetermine generalization of classification of binary codes, in order to simplify the structure of the subject area and to increase the diversity of binary codes, in particular, for arithmetic operations with binary numbers.
2. The data about the vector of the code D(x) that are presented by dependencies (7) in algebraic or bitmap view are general representation of binary codes for all combinatorial systems P(2, b i ) that allows changing the system of binary codes using a single universal table of the data on the vector of the code D(x).
Thus, the studies of this work may become a component of the technology of designing electronic computing systems, because: -they expand the apparatus of obtaining recurrent binary codes for their application in the information technology; -they provide a possibility to control the selection of the code at the stage of designing a computing device; -they help predict the impact of the implementation of the selected code in the solution of problems of the information systems; -they minimize hardware costs associated with the selection of the system of binary code for the calculation.

Reduction of thesaurus of parallel adder of binary codes without inter digit carry
An instance P(2, b i ) of the class P(2, n) is selected on a ring structure using original block b i of complete combinatorial system with repetition (Table 1).This means that the principle of setting up the system of binary codes with its code-beginning is within the range of complete combinatorial system with repetition (Table 1).Since the location of the principle of obtaining binary codes is defined, the thesaurus of parallel adder of binary codes without carry is necessary to rewrite (Table 19).We see from Table 17 that the number of concepts of thesaurus of the adder of binary codes is less in comparison with the number of concepts of thesaurus of the adder of the Galois field codes, which, however, does not affect the quality of the construction of the adder of binary codes without carry and reliability of the computational results in this adder.The prospect of further review of the operation of summation of binary codes without carry is to use it in other digital technologies, in particular, in the methods of cryptography.
12. Conclusions 1.It was established that the properties of recursive method of the synthesis of binary codes allow focusing the principle of building codes in the range of complete combinatorial system with repetition, which ensures reduction of the thesaurus of the parallel adder of binary codes without carry.
2. It was found that the system of binary codes, formed by means of any initial code of complete combinatorial system with Adder's scheme depth (dt) The digit capasity of adder (n) Fig. 7. Dynamics of increasing the depth of the scheme of the parallel adder without inter digit carry (AWC) and parallel adder with a parallel way of carry CLA repetition, has a ring structure, which allows using any system of binary codes in the operation of adding codes without carry.
3. We discovered that the calculation of the signals of the sum in the scheme of a parallel adder of binary codes without carry is performed by the script of the algorithm of pairing.Thus, the complexity of the algorithm of calculation of the signals of the sum of a parallel adder of binary codes without carry is O(log n) and it is logarithmic -the time of algorithm realization increases by the logarithmic law with the increase in the digit capacity of numbers n.where n is the digit capacity of a number.
6.It was established that the productivity of computing of signals of the sum by the parallel adder of binary codes without carry and by the parallel adder with a parallel way of carry CLA (Carry Look-ahead Adder) is approximately the same.Thus, the complexity of the algorithm of calculation of signals of the sum and the carry of the CLA adder is also subject to the logarithmic law.And since the adders of binary codes have no hardware costs for the carries between the digits, obvious is reduction in energy consumption, decrease in the heat release by a computing device (integrated circuit) based on such adders.

8 .
It follows from the property 6 that the number of recurrent binary codes in the system P(2, b i ) is determined by the number n b 2 1, = − Character representation of the expressions of the 4-bit codes a -А(х), b -D(x), c -C(х) of the instances Table 6

Fig. 1 . 4 -
Fig. 1. 4-digit adder of binary codes for the first bit of the sum C(х): a -combination scheme of the first digit of the adder; b -scheme of the adder of the first bit presented by complex logic

Fig. 2 .Fig. 3 .
Fig. 2. Scheme of the first digit of the 8-bit adder of binary codes without carry on the logical elements AND and XOR

Fig. 4 .
Fig. 4. Structure of the functional connection of the control output of the decoder with a string of intermediate coefficients d ji of the logical vector D'(x) using the multiplexer in the scheme of the 4-bit adder of binary codes

4 . 5 .
It was established that the logic of the work of the adder of binary codes without carry corresponds to the computation protocol of the parallel adder without carry.A number of options of adding b of multi digit parallel adder of binary codes without carry is It was established that the range of adding of numbers of the adder of binary codes without carry is:x D +y D =<2 n -2,

Table 1 4
-bit binary codes in lexicographical order

Table 9
Program procedure D'(x) over the 4-bit code А(х) for all combinatorial systems P(2, b i ) in the bitmap representation

Table 16
Computation protocol of the 4-bit adder of binary codes without carry for the initial code fragment -1111 3 =8)

Table 18
Dynamics of increasing the depth of the scheme of parallel adder with a parallel way of carry with increase in the digit capacity of the adder

Table 19
Comparison of the thesaurus of the Galois field codes and the adder of binary codes