DOI: https://doi.org/10.15587/1729-4061.2016.75596

Optimal synthesis of digital counters in the fibonacci codes with the minimal form of representation

Oleksiy Borysenko, Igor Kulyk, Svitlana Matsenko, Olga Berezhna, Aleksandr Matsenko

Abstract


At present, requirements for speed performance and noise immunity in the work of the counters increase. Among the existing structures, the Fibonacci counters meet such requirements. Their drawback is transfer while calculating from the minimal form of representation of the Fibonacci numbers to the maximal form and, consequently, to the use of operations of convolution and deconvolution, which decreases speed, noise immunity and increases required hardware expenses.

We propose for the Fibonacci counters to use only minimal form of representation of the Fibonacci numbers, which excludes operations of convolution and deconvolution. Based on it, the method of the Fibonacci calculation in the minimal form is developed and its logical model is built in the form of a set of logical operations, whose fulfillment leads to the Fibonacci calculation. It gives the possibility to design the method of synthesis of the Fibonacci counters with the optimal ratio of performance speed, noise immunity and amount of hardware expenses for specific conditions of its work.

The advantage of the Fibonacci counters with the minimal form is their increased noise immunity. It is due to both the nature of the Fibonacci calculation itself, which works in the excess codes, and to the absence of transfers to the maximal form, where it is permitted to have the forbidden combinations. In this case, the probability of detecting errors grows with an increase in the number of bits of counter.


Keywords


Fibonacci numbers; minimal form; Fibonacci counters; noise immunity; high performance speed

References


Goryachev, A. E., Degtyar, S. A. (2012). Metod generacii perestanovok na osnove faktorialnyx chisel s ispolzovaniem dopolnyayushhego massiva. Visnik Sumskogo derzhavnogo unіversitetu. Serіya Tehnichni nauki, 4, 86–93.

Borysenko, O. A., Kalashnikov, V. V., Protasova, T. A., Kalashnikova, N. I.; Silva, R. N. (Ed.) (2014). A New Approach to the Classification of Positional Numeral Systems. Series Frontiers of Artificial Intelligence and Applications (FAIA). IOS Press (The Netherlands), 262, 441–450.

Vorobev, N. N. (1969). Chisla Fibonachchi. Мoscow: Nauka, 144.

Monteiro, P., Newcomb, R. (1976). Minimal and Maximal Fibonacci Representations: Boolean Generation. The Fibonacci Quarterly, 14 (1), 613–638.

Vajda, S. (1989). Fibonacci & Lucas Numbers, and the Golden Section. Ellis Horwood limited, 192.

Staxov, A. P. (1977). Vvedenie v algoritmicheskuyu teoriyu izmerenij. Мoscow: Sov. radio, 288.

Staxov, A. P. (2012). Kody Fibonachchi i zolotoj proporcii kak alternativa dvoichnoj sistemy schisleniya. Chast 1. Germany: Academic Publishing, 305.

Gupta, N., Agarval, A., Goyal, G. (2015). United States Patent No. US8983023 B2. Digital Self-Gated Binary Counter. No. US 13/935,552; declared: 04.07.2013; published: 17.03.2015, 23.

Yeh, C.-H., Parhami, B., Wang, Y. (2000). Designs of Counters with Near Minimal Counting/Sampling Period and Hardware Complexity. Pacific Grove, CA, USA, 894–898. doi: 10.1109/acssc.2000.910642

Thamaraiselvan, K., Gayathri, C., Divya, N. (2013). A High Speed CMOS Parallel Counter Using Pipeline Partitioning. International Journal of Engineering Research, 2 (8), 491–495.

Bindu, S., Vineeth, V., Paulin, J. (2015). A Review on High Speed CMOS Counter Using Altera MAX300A. International Journal of Advanced Research in Computer and Communication Engineering, 4 (12), 589–592. doi: 10.17148/ijarcce.2015.412140

Azarov, O. D., Chernyak, O. І., Murashhenko, O. G. (2015). Shvidkodіyuchij reversivnij fіbonachchіеvij lіchilnik. Іnformacіjnі texnologіі ta komp’yuterna іnzhenerіya, 1, 27–32.

Azarov, O. D., Chernyak, O. І. (2015). Metod shvidkodіyuchoі obernenoі lіchbi z lіnіjnim zrostannyam aparaturnix vitrat pri naroshhuvannі rozryadnostі. Visnyk Vinnyc'kogo politehnichnogo instytutu, 2 (119), 57–61.

Azarov, O. D., Chernyak, O. І., Murashhenko, O. G. (2014). Metod pobudovi shvidkodіyuchix fіbonachchіеvix lіchilnikіv. Problemy informatyzacii' ta upravlinnja, 2 (46), 5–8.

Borysenko, O. A., Stahov, O. P. (2014). Pat. na vynahid № 104939 U Ukrajna. MPK H03K 23/00 (2014.01). Pereshkodostijkyj lichyl'nyk impul'siv Borysenko-Stahova. № 201210506; zajavl. 05.09.2012; opubl. 25.03.2014, Bjul. № 6.


GOST Style Citations


1. Goryachev, A. E. Metod generacii perestanovok na osnove faktorialnyx chisel s ispolzovaniem dopolnyayushhego massiva [Text] / A. E. Goryachev, S. A. Degtyar // Visnik Sumskogo derzhavnogo unіversitetu. Serіya Tehnichni nauki. – 2012. – Issue 4. – P. 86–93.

2. Borysenko, O. A. A New Approach to the Classification of Positional Numeral Systems [Text] / O. A. Borisenko, V. V. Kalashnikov, T. A. Protasova, N. I. Kalashnikova; R. N. Silva (Ed.) // Series Frontiers of Artificial Intelligence and Applications (FAIA). – IOS Press (The Netherlands), 2014. − Vol. 262. − P. 441–450.

3. Vorobev, N. N. Chisla Fibonachchi [Text] / N. N. Vorobev. – Мoscow: Nauka, 1969. – 144 p.

4. Monteiro, P. Minimal and Maximal Fibonacci Representations: Boolean Generation [Text] / P. Monteiro, R. Newcomb // The Fibonacci Quarterly. – 1976. – Vol. 14, Issue 1. – Р. 613–638.

5. Vajda, S. Fibonacci & Lucas Numbers, and the Golden Section [Text] / S. Vajda. – Ellis Horwood limited, 1989. – 192 p.

6. Staxov, A. P. Vvedenie v algoritmicheskuyu teoriyu izmerenij [Text] / A. P. Staxov. – Мoscow: Sov. radio, 1977. – 288 p.

7. Staxov, A. P. Kody Fibonachchi i zolotoj proporcii kak alternativa dvoichnoj sistemy schisleniya. Chast 1 [Text] / A. P. Staxov. – Germany: Academic Publishing, 2012. – 305 p.

8. United States Patent No. US8983023 B2. Digital Self-Gated Binary Counter [Text] / Gupta N., Agarval A., Goyal G. – No. US 13/935,552; declared: 04.07.2013; published: 17.03.2015. – 23 p.

9. Yeh, C.-H. Designs of Counters with Near Minimal Counting/Sampling Period and Hardware Complexity [Text]: conference / C.-H. Yeh, B. Parhami, Y. Wang. – Pacific Grove, CA, USA, 2000. – P. 894–898. doi: 10.1109/acssc.2000.910642

10. Thamaraiselvan, K. A High Speed CMOS Parallel Counter Using Pipeline Partitioning [Text] / K. Thamaraiselvan, C. Gayathri, N. Divya // International Journal of Engineering Research. – 2013. – Vol. 2, Issue 8. – Р. 491–495.

11. Bindu, S. A Review on High Speed CMOS Counter Using Altera MAX300A [Text] / S. Bindu, V. Vineeth, J. Paulin // International Journal of Advanced Research in Computer and Communication Engineering. – 2015. − Vol. 4, Issue 12. – P. 589–592. doi: 10.17148/ijarcce.2015.412140

12. Azarov, O. D. Shvidkodіyuchij reversivnij fіbonachchіеvij lіchilnik [Text] / O. D. Azarov, O. І. Chernyak, O. G. Murashhenko // Іnformacіjnі texnologіі ta komp’yuterna іnzhenerіya. – 2015. – Issue 1. – P. 27–32.

13. Azarov, O. D. Metod shvidkodіyuchoі obernenoі lіchbi z lіnіjnim zrostannyam aparaturnix vitrat pri naroshhuvannі rozryadnostі [Text] / O. D. Azarov, O. І. Chernyak // Visnyk Vinnyc'kogo politehnichnogo instytutu. – 2015. – Issue 2 (119). – P. 57–61.

14. Azarov, O. D. Metod pobudovi shvidkodіyuchix fіbonachchіеvix lіchilnikіv [Text] / O. D. Azarov, O. І. Chernyak, O. G. Murashhenko // Problemy informatyzacii' ta upravlinnja. – 2014. – Issue 2 (46). – P. 5–8.

15. Pat. na vynahid № 104939 U Ukrajna. MPK H03K 23/00 (2014.01). Pereshkodostijkyj lichyl'nyk impul'siv Borysenko-Stahova [Text] / Borysenko O. A., Stahov O. P.; zajavnyk ta patentovlasnyk Sums'kyj derzh. un-t. – № 201210506; zajavl. 05.09.2012; opubl. 25.03.2014, Bjul. № 6.



 

Cited-by:

1. Development of the Fibonacci-Octal Error Detection Code for Telecommunication Systems
Oleksii Borysenko, Svitlana Matsenko, Sandis Spolitis, Vjaceslavs Bobrovs
2020 24th International Conference Electronics  First page: 1  Year: 2020  
doi: 10.1109/IEEECONF49502.2020.9141620





Copyright (c) 2016 Olexiy Borysenko, Lubomyr Petryshyn, Svitlana Matsenko, Igor Kulyk, Olga Berezhna

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.

ISSN (print) 1729-3774, ISSN (on-line) 1729-4061