EVENT PROCESSING MODEL FOR SIMULATION OF REAL-TIME LOGIC CONTROL DEVICES

Abstract

Among modern technical systems, logical control and communication devices with touch control panels play an increasingly important role. In such devices the duration of controlling events is important. On the other hand, a person cannot exactly control the durability of the event when pressing and holding a panel. Based on this, a control device (control unit) must properly respond to external events of unknown durability. Thus, when designing a real-time system, it’s required to express metric time in terms of the automation clock because the transitions between the automata states directly depend on the metric time aspect. The purpose of this article is to introduce a new events class used in real-time device simulation – the events with minimal duration. The object of research is real-time device control algorithms. The subject of research is event-based automatic models described by the hardware description languages. The article analyzes the issue of simulation real-time devices using the state machine template in hardware description languages. The classification of events as finite state machine interaction with the external environment models is analyzed. A new type of event and a class of devices whose functionality depends on such factors are introduced. It is shown that such events are widespread in various digital devices and real-time systems. A new type of FSM transition is proposed for the temporal state diagram as digital systems design canonical model. The considered models are illustrated by simulations and timing diagrams analysis. For the proposed model, different cases of the duration of the event have been considered and the corresponding processes of the machine’s reaction to them are as follows: the external event lasts exactly as long as required in the specification; the external event lasts less than required; the external event lasts longer than required; no external event occurs. All possible processes are illustrated with timing diagrams with detailed explanations and hardware description language code examples. A description of the device model fragment using the Verilog synthesizable subset is given.