Design and self-diagnostics of cyberphysical control devices on SOC platform

Authors

DOI:

https://doi.org/10.30837/ITSSI.2023.26.122

Keywords:

cyber-physical systems; embedded systems; logic control; system-on-chip design; FPGA; CAD; SoC self-testing; C programming language

Abstract

The subject of research in this article is models, methods, and procedures for designing and self-diagnosing automated models of logic control devices implemented in SoCs. The object of work is the procedures for automated design and diagnosis of digital devices on the SoC technology platform. The aim of the study is to develop models and procedures for designing and self-testing in the cycle of automated design of automatic logic control systems on the SoC technology platform, which will significantly increase the reliability of their operation. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of the SoC; improvement of the procedures for designing and testing software and hardware systems based on SoC; further development of procedures for automated design, verification, and diagnosis of cyber-physical logic control systems using programming languages and hardware description languages; implementation of the procedure for hardware self-testing of control automata on the SoC technology platform. The following methods are implemented: synthesis of control automata based on graph models, implementation of control automata models in the C programming language using an automata template, diagnostic experiment by traversing the automata transition graph. Results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of a cyber-physical logic control system was designed. The practical implementation was carried out on the basis of the Vivado/Vitis/Vitis HLS CAD toolkit. The method of hardware self-testing of control automata on the technological platform of SoC ZYNQ-7000 was implemented. Conclusions. The article analyzes the principles of designing embedded cyber-physical systems implemented in system-on-chip. The principles of building verification systems and embedded self-diagnostics of system-on-chip systems containing software and hardware are considered. The developed methods are tested on a model of a traffic light logic control device on the SoC FPGA platform of the ZYNQ-7000 family by Xilinx. The Moore's control automaton is implemented in the PL block in the C programming language, and the operational automaton is implemented in the PS block. During the organization of the self-diagnosis process, a non-destructive diagnostic experiment was performed by traversing all arcs of the transition graph, starting from the initial vertex. In this case, the tester was an operational automaton, the reference logic and time values of which were stored in the memory of the PS unit. Visual observation of the diagnostic experiment was carried out using the LED panel of the ZedBoard board.

Author Biographies

Alexander Shkil, Kharkiv National University of Radio Electronics

PhD (Engineering Sciences), Associate Professor, Associated Professor of Design Automation Department

Dariia Rakhlis, Kharkiv National University of Radio Electronics

PhD (Engineering Sciences), Associate Professor, Associated Professor of Design Automation Department

Inna Filippenko, Kharkiv National University of Radio Electronics

PhD (Engineering Sciences), Associated Professor of Design Automation Department

Valentyn Korniienko, Kharkiv National University of Radio Electronics

PhD Student of Design Automation Department

References

Список літератури

Lee E. A., Seshia S. A. Introduction to embedded systems: A cyber-physical system approach. UC Berkeley, 2011. 499 p. URL: https://ptolemy.berkeley.edu/books/leeseshia/releases/LeeSeshia_DigitalV1_08.pdf

Greaves D. Modern system-on-chip design on ARM. Arm Education Media, 2021. 608 p. URL: https://armkeil.blob.core.windows.net/developer/Files/pdf/ebook/arm-modern-soc.pdf

Teich J. Hardware software codesign: the past, the present, and predicting the future. Proc. IEEE, Vol. 100. 2012. P. 1411–1430. DOI: 10.1109/JPROC.2011.2182009

Bailey B., Martin G., Piziali A. ESL design and verification: A prescription for electronic system level methodology. Morgan Kaufmann Publishers Inc. 2007. P. 113–138. DOI: 10.1016/B978-012373551-5/50068-X

Shalyto A. A. Software automation design: algorithmization and programming of problems of logical control. Journal of Computer and System Sciences International. Vol. 39, No. 6. 2000. P. 899–916. URL: https://www.researchgate.net/publication/297443303_Software_automaton_design_Algorithmization_and_programming_of_problems_of_logical_control

Alur R., Dill D.L. A theory of timed automata. Theoretical Computer Science. Vol.126, № 2. 1994. P. 183–235. DOI: 10.1016/0304-3975(94)90010-8

Zhigulin M. Yevtushenko N., Maag S., Cavalli A. R. FSM-based test derivation strategies for systems with time-outs. Proceedings of the 11th International Conference on Quality Software (QSIC 2011), Madrid, Spain, 2011. P. 141–149. DOI:10.1109/QSIC.2011.30

El-Fakih K., Yevtushenko N., Simão A. A practical approach for testing timed deterministic finite state machines with single clock. Science of Computer Programming. Elsevier. Vol. 80. 2014. P. 343–355. DOI: 10.1016/j.scico.2013.09.008

Mіrosсhnyk M., Shkil A., Kulak E., Rakhlis D., Filippenko I., Hoha M., Malakhov M., Serhiienko V. Design of real-time logic control system on FPGA. Proceedings of 2019 IEEE East-West Design & Test Symposium (EWDTS’19), September 13-16, Batumi, Georgia, 2019. P. 488–491. DOI: 10.1109/EWDTS.2019.8884387

Mіrosсhnyk M. A., Shkil A. S., Kulak E. N., Rakhlis D. Y., Mіroshnyk A. M., Malahov N. V. Design timed FSM with VHDL Moore pattern. Radio Electronics, Computer Science, Control. 2020. №2 (53). P. 137–148. DOI: 10.15588/1607-3274-2020-2-14

Мірошник М. А. Проектування діагностичної інфраструктури обчислювальних систем та пристроїв на ПЛІС: монографія. Х.: ХУПС, 2012. 188 с. URL: http://lib.kart.edu.ua/bitstream/123456789/7162/1/%D0%9D%D0%B0%D0%B2%D1%87%D0%B0%D0%BB%D1%8C%D0%BD%D0%B8%D0%B9%20%D0%BF%D0%BE%D1%81%D1%96%D0%B1%D0%BD%D0%B8%D0%BA.pdf

Chi Y., Guo L., Lau J., Choi Y. K., Wang J., Cong J. Extending high-level synthesis for task-parallel programs. Proceedings of 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 28 February - 2 March 2021. 225 р. DOI: 10.1145/3431920.3439470

Gniazdowski T. et al. High-performance lightweight HLS generator module of normally distributed random numbers in FPGAs. Electronics. Vol. 12, No. 22. 2023. 4667 р. DOI: 10.3390/electronics12224667

Caba J., Rincón F., Barba J., De la Torre J. A., López J. C. FPGA-based solution for on-board verification of hardware modules using HLS. Electronics. Vol. 9, No. 12. 2020. 2024 р. DOI: 10.3390/electronics9122024

Roozmeh M. High performance computing via high level synthesis, Xilinx FPGA. PhD thesis. Turin, 2018. 125 p. DOI: 10.6092/POLITO/PORTO/2710706

Heyden M. High Level Synthesis for ASIC and FPGA: master thesis. Sweden, Lund, 2023. 47 p. URL: https://lup.lub.lu.se/student-papers/record/9126669/file/9128084.pdf (дата звернення: 10.11.2023).

Crockett L. H., Elliot R. A., Enderwitz M. A., Stewart R. W. The Zynq Book: Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000. All Programmable SoC. Strathclyde Academic Media, 2014. P. 484. URL: https://is.muni.cz/el/1433/jaro2015/PV191/um/The_Zynq_Book_ebook.pdf (дата звернення: 17.09.2023).

References

Lee E. A., Seshia S. A. "Introduction to embedded systems: A cyber-physical system approach, Berkeley". 2011. 499 p. available at: https://ptolemy.berkeley.edu/books/leeseshia/releases/LeeSeshia_DigitalV1_08.pdf

Greaves D. "Modern system-on-chip design on ARM, Arm Education Media". 2021. 608 p. available at: https://armkeil.blob.core.windows.net/developer/Files/pdf/ebook/arm-modern-soc.pdf

Teich, J. (2012), "Hardware/software codesign: the past, the present, and predicting the future", Proc. IEEE, Vol. 100. P. 1411–1430. DOI: 10.1109/JPROC.2011.2182009

Bailey, B., Martin, G., Piziali, A. (2007), "ESL design and verification: A prescription for electronic system level methodology", Morgan Kaufmann Publishers Inc., P. 113–138. DOI: 10.1016/B978-012373551-5/50068-X

Shalyto, A. A. "Software automation design: algorithmization and programming of problems of logical control", Journal of Computer and System Sciences International, Vol. 39, No. 6, 2000. P. 899–916. available at: https://www.researchgate.net/publication/297443303_Software_automaton_design_Algorithmization_and_programming_of_problems_of_logical_control

Alur, R., Dill, D.L. (1994), "A theory of timed automata", Theoretical Computer Science, Vol.126, № 2, P. 183–235. DOI: 10.1016/0304-3975(94)90010-8

Zhigulin, M. Yevtushenko, N., Maag, S., Cavalli, A. R. (2011), "FSM-based test derivation strategies for systems with time-outs". Proceedings of the 11th International Conference on Quality Software (QSIC 2011), Madrid, Spain, P. 141–149. DOI:10.1109/QSIC.2011.30

El-Fakih, K., Yevtushenko, N., Simão, A. (2014), "A practical approach for testing timed deterministic finite state machines with single clock", Science of Computer Programming, Elsevier, Vol. 80, P. 343–355. DOI: 10.1016/j.scico.2013.09.008

Mіrosсhnyk, M., Shkil, A., Kulak, E., Rakhlis, D., Filippenko, I., Hoha, M., Malakhov, M., Serhiienko, V. (2019), "Design of real-time logic control system on FPGA". Proceedings of 2019 IEEE East-West Design & Test Symposium (EWDTS’19), September 13-16, Batumi, Georgia, P. 488–491. DOI: 10.1109/EWDTS.2019.8884387

Mіrosсhnyk, M. A., Shkil, A. S., Kulak, E. N., Rakhlis, D. Y., Mіroshnyk, A. M., Malahov, N. V. (2020), "Design timed FSM with VHDL Moore pattern", Radio Electronics, Computer Science, Control, №2 (53), P. 137–148. DOI: 10.15588/1607-3274-2020-2-14

Mіrosсhnyk, М. А. (2012), "Design of diagnostic infrastructure of computing systems and devices on FPGA" ["Proektuvannya diagnosty`chnoyi infrastruktury` obchy`slyuval`ny`x sy`stem ta pry`stroyiv na PLIS"], monograph, Kharkiv, 331 p. available at: http://lib.kart.edu.ua/bitstream/123456789/7162/1/%D0%9D%D0%B0%D0%B2%D1%87%D0%B0%D0%BB%D1%8C%D0%BD%D0%B8%D0%B9%20%D0%BF%D0%BE%D1%81%D1%96%D0%B1%D0%BD%D0%B8%D0%BA.pdf

Chi, Y., Guo, L., Lau, J., Choi, Y. K., Wang, J., Cong, J. (2021), "Extending high-level synthesis for task-parallel programs". Proceedings of 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 225 р. DOI: 10.1145/3431920.3439470

Gniazdowski, T. et al. (2023), "High-performance lightweight HLS generator module of normally distributed random numbers in FPGAs", Electronics, Vol. 12, No. 22, 4667 р. DOI: 10.3390/electronics12224667

Caba, J., Rincón, F., Barba, J., De la Torre, J. A., López, J. C. (2020), "FPGA-based solution for on-board verification of hardware modules using HLS", Electronics, Vol. 9, No. 12, P. 2024. DOI: 10.3390/electronics9122024

Roozmeh, M. (2018), "High performance computing via high level synthesis". Xilinx FPGA. PhD thesis, Turin, 125 р. DOI: 10.6092/POLITO/PORTO/2710706

Heyden, M. "High Level Synthesis for ASIC and FPGA": master thesis. Sweden, Lund, 2023. 47 p. available at: https://lup.lub.lu.se/student-papers/record/9126669/file/9128084.pdf (last accessed: 10.11.2023).

Crockett, L. H., Elliot, R. A., Enderwitz, M. A., Stewart, R. W. "The Zynq Book: Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000. All Programmable SoC, Strathclyde Academic Media", 2014. P. 484. available at: https://is.muni.cz/el/1433/jaro2015/PV191/um/The_Zynq_Book_ebook.pdf (last accessed: 17.09.2023).

Published

2023-12-27

How to Cite

Shkil, A., Rakhlis, D., Filippenko, I., & Korniienko, V. (2023). Design and self-diagnostics of cyberphysical control devices on SOC platform. INNOVATIVE TECHNOLOGIES AND SCIENTIFIC SOLUTIONS FOR INDUSTRIES, (4(26), 122–134. https://doi.org/10.30837/ITSSI.2023.26.122