VLSI-based synthesis of Moore finite-state-machines targeting telecommunications systems

Abstract

The optimization methods of the logic circuit of Moore finite-state-machine are proposed. These methods are based on the existence of pseudo equivalent states of Moore finite-state-machine, wide fan-in of PAL macrocells, and free resources of embedded memory blocks. The methods are oriented on hypothetical VLSI microcircuits based on CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm of choice of the best model of finite-state-machine for given conditions is proposed. The examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated. The analysis of the effectiveness of proposed methods showed that optimal in the given conditions method always permits a decrease of the hardware amount in comparison with earlier known methods of the Moore finite-state-machine design. This decrease in hardware does not lead to a decrease in the performance of the control unit. Moreover, there are some special cases, when some other models of Moore finite-state-machine are more effective. The proposed methods can be modified for real CPLDs, where embedded memory blocks are absent. In this case, the system of microoperations is implemented using PAL macrocells too. The same effectiveness of proposed methods should be tested for both cases of FPGA with embedded memory blocks and for CPLD CoolRunner based on PLA technology. The proposed methods should be modified to meet the specific requirements of these chips.