Data structures for deductive simulation of HDL conditional operators
DOI:
https://doi.org/10.30837/ITSSI.2023.25.098Keywords:
HDL-model; structural-functional model; deductive fault simulation; cubic coverage; truth table; Q-vectorAbstract
The subject of research in the article is qubit-vector models for combinational circuits’ description and procedures for faults deductive simulation based on these models. The object of research is the processes of diagnostic support creation for digital systems based on the usage of vector qubit data. The purpose of the work is to increase the speed and quality of diagnostic support creation for digital devices by creating optimal data structures and deductive fault simulation procedures based on structural-functional models of combinational circuits. The following tasks are solved in the article: analysis of concurrent and sequential conditional operators of hardware description languages and schematic structures into which they are synthesized; development of the procedure for the truth tables (Q-vectors) formation for schematic structures presented by HDL; development of an universal data structure for cubic and analytical deductive faults simulation; vector models improvement of qubit representation of structures and components of digital systems based on address coding of input signals to increase the manufacturability and speed of faults simulation; development of the procedure for obtaining Boolean derivatives by permuting the lines of the truth tables (Q-vectors) and using the XOR operation; development of a data structure for deductive fault simulation based on the cubic representation of digital circuit components. The following methods are used: deductive, cubic, deductive-parallel simulation of faults, faults simulation by deductive Q-vectors. The following results were obtained: the equivalence of concurrent and sequential conditional operators, as well as their schematic implementation in the form of multiplexers, was shown; method of obtaining truth tables of the synthesized circuit structure using TestBench (Xilinx ISE) was proposed; different technologies and data structures of deductive fault simulation for tabular, analytical and qubit methods of digital circuits description were considered; the software implementation of faults cubic deductive simulation is considered and the equivalence of the obtained results for the multiplexers circuits (MUX 2-in-1 and MUX 4-in-1) using the DCP software product was demonstrated. Conclusions: a new Q-method of interpretative faults simulation of digital circuit is proposed, which is characterized by the usage of compact Q-vectors instead of truth tables, which makes it possible to significantly increase the analysis speed due to the addressable formation of the functional primitives outputs and reduce the volume of data structures, which practically makes the method competitive with compilative simulation technologies.
References
Список літератури
Abramovici M. A., Breuer A. М., Friedman D. Digital system testing and testable design. Comp. Sc. Press., 1998. 652 p.
Armstrong D. B. A deductive method of simulating faults in logic circuits. IEEE Trans. on Computers. Vol. № 5. 1972. P. 464–471. DOI: 10.1109/T-C.1972.223542
Шкиль А. С., Хаханов В. И., Ханько В. В. Дедуктивный метод кубического моделирования неисправностей цифровых устройств. Радиоэлектроника и информатика. 1999. № 1(6). С. 77–84. URL: https://openarchive.nure.ua/bitstreams/1e30e364-445b-488f-97ea-9394cd98e7e2/download
Хаханов В. И., Ковалев Е. В., Джахирул Х. М., Мехеди Масуд М. Д. Кубическое моделирование неисправностей цифровых проектов на основе FPGA, CPLD. Радиоэлектроника и информатика. 1999. № 4. С. 64–71.
Хаханова А. В., Хаханов В. І., Чумаченко С. В., Литвинова Є. І., Рахліс Д. Ю. Векторні моделі логіки і структури для тестування та моделювання цифрових схем. Радіоелектроніка. Інформатика. Управління. Запоріжжя: ЗНТУ. 2021. №3. C. 69–85. DOI: 10.15588/1607-3274-2021-3-7
Liu T., Yu T., Wang S., Cai S. An efficient degraded deductive fault simulator for small-delay defects. Institute of Electrical and Electronics Engineers (IEEE Access). 2020. Vol. 8. P. 855–862. DOI: 10.1109/ACCESS.2020.3037292
Kaja E., Gerlin N., Rivas L., Bora M.K., Devarajegowda K., Ecker W. MetaFS: model-driven fault simulation. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 19-21 Oct. 2022. P. 1–8. DOI:10.1109/DFT56152.2022.9962369
Gupta I. Stuck at fault testing in combinational circuits using FPGA. Proceedings of emerging trends and technologies on intelligent systems. Advances in Intelligent Systems and Computing. Springer, Singapore. Noida, India, Vol 1371. P. 275–284. DOI: 10.1007/978-981-16-3097-2_23
Higami Y., Yamauchi T., Inamoto T., Wang S., Takahashi H., Saluja K. K. Machine learning based fault diagnosis for stuck-at faults and bridging faults. 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC’22), Phuket, Thailand, 2022. P. 477–480. DOI: 10.1109/ITC-CSCC55581.2022.9894966
Soham R., Millican S., Agrawal V. Training neural network for machine intelligence in automatic test pattern generator.
th International Conference on VLSI Design and 20th International Conference on Embedded Systems (VLSID’21), 2021, Guwahati, India. P. 16–32. DOI: 10.1109/VLSID51830.2021.00059
Nirmalraj T. Radhakrishnan S., Pandiyan S. K. Automatic diagnosis of single fault ininterconnecttesting of SRAM‐based FPGA. IET Computers & Digital Techniques. John Wiley& Sons Ltd. 2021. №15 (5). P. 362–371. DOI: 10.1049/cdt2.12028
Хаханов В. И., Ктейман Хассан, Парфентий А. Н., Хаханова И. В. HFS-процессор аппаратного моделирования неисправностей цифровых проектов. АСУ и приборы автоматики. 2007. № 1 (134). С. 93–108.
Gharibi W., Hahanova A., Hahanov V., Chumachenko S., Litvinova E., Hahanov I. Vector-logic synthesis of deductive matrices for fault simulation. Èlektronic modeling. 2023. №45 (2). P. 16–33. DOI: 10.15407/emodel.45.02.016.
Pong P. С. RTL Hardware design using VHDL: coding for efficiency, portability, and scalability. Wiley-IEEE Press, 2006. 694 p. DOI: 10.1002/0471786411
Shkil A.S., Miroshnyk M., Kulak E., Filippenko I., Kucherenko D., Grebenyuk A. Synchronizing Sequences for Verification of Finite State Machines. 9th International IEEE Conference Dependable Systems, Services and Technologies, DESSERT’2018, Ukraine, Kyiv, 2018. P. 226–230. DOI: 10.1109/UkrMiCo47782.2019.9165509
Шкиль А. С., Кривуля Г. Ф. Автоматизация получения булевых разностей. АСУ и приборы автоматики. 1981. Вып. 59. С. 73–78.
Хаханов В. И., Емельянов И. В., Любарский М. М., Чумаченко С. В., Литвинова Е. И., Бани А. Т. Кубитный метод дедуктивного анализа неисправностей для логических схем. Электронное моделирование. 2017. Т. 39(6). С. 59–91.
References
Abramovici, M. A., Breuer, A. М., Friedman, D. (1998), Digital system testing and testable design, Comp. Sc. Press, 652 p.
Armstrong, D. B. (1972), "A deductive method of simulating faults in logic circuits", IEEE Trans. on Computers, Vol. № 5, P. 464–471. DOI: 10.1109/T-C.1972.223542
Shkil, А. С., Hahanov, V. І., Han’ko, V. V. (1999), "Deductive method of cubic faults simulation of digital devices" ["Deduktivnyj metod kubicheskogo modelirovanija neispravnostej cifrovyh ustrojstv"], Radioelectronics and informatics, № 1(6), P. 77–84, available at: https://openarchive.nure.ua/bitstreams/1e30e364-445b-488f-97ea-9394cd98e7e2/download
Hahanov, V. I., Kovalev, Е. V., Djahirul, Hak H. M., Mehedi, Masud M.D. (1999), "Cubic fault simulation of digital systems based on FPGA, CPLD" ["Kubicheskoe modelirovanie neispravnostej cifrovyh proektov na osnove FPGA, CPLD"], Radioelectronics and informatics, № 4, P. 64–71.
Hahanova, А. V., Hahanov, V. І., Chumachenko, S. V., Litvinova, E. І., Rakhlis, D. Y. (2021), "Vector-driven logic and structure for testing and deductive fault simulation" ["Vektorni modeli logiky` i struktury` dlya testuvannya ta modelyuvannya cy`frovy`x sxe"], Radio Electronics, Computer Science, Control, Zaporizhzhia: ZNТU, №3, P.69–85. DOI: 10.15588/1607-3274-2021-3-7
Liu, T., Yu, T., Wang, S., Cai, S. (2020), "An efficient degraded deductive fault simulator for small-delay defects", Institute of Electrical and Electronics Engineers (IEEE Access), Vol. 8, P. 855–862. DOI: 10.1109/ACCESS.2020.3037292
Kaja, E., Gerlin, N., Rivas, L., Bora, M. K., Devarajegowda, K., Ecker, W. (2022), "MetaFS: model-driven fault simulation", IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), P. 1–8. DOI:10.1109/DFT56152.2022.9962369
Gupta, I. (2021), "Stuck at fault testing in combinational circuits using FPGA", Proceedings of emerging trends and technologies on intelligent systems, Advances in Intelligent Systems and Computing, Springer, Singapore, Noida, India, Vol. 1371, P. 275–284. DOI: 10.1007/978-981-16-3097-2_23
Higami, Y., Yamauchi, T., Inamoto, T., Wang, S., Takahashi, H., Saluja, K. K. (2022), "Machine learning based fault diagnosis for stuck-at faults and bridging faults", 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC’22), Phuket, Thailand, P. 477–480. DOI: 10.1109/ITC-CSCC55581.2022.9894966
Soham, R., Millican, S., Agrawal, V. (2021), "Training neural network for machine intelligence in automatic test pattern generator", 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems (VLSID’21), Guwahati, India, P. 16–32. DOI: 10.1109/VLSID51830.2021.00059
Nirmalraj, T. Radhakrishnan, S., Pandiyan, S. K. (2021), "Automatic diagnosis of single fault ininterconnecttesting of SRAM‐based FPGA", IET Computers & Digital Techniques, John Wiley&Sons, №15 (5), P. 362–371. DOI: 10.1049/cdt2.12028
Hahanov V. I., Kteyman H., Parfentiy A. N., Hahanova I. V. (2007), "HFS-processor for hardware fault simulation of digital projects" ["HFS-processor apparatnogo modelirovanija neispravnostej cifrovyh proektov"], ACS and automation devices, № 1 (134), P. 93–108.
Hahanov V., Gharibi W., Hahanova A., Chumachenko S., Litvinova E., Hahanov I. (2023), "Vector-logic synthesis of deductive matrices for fault simulation", Electronic simulation, Vol. 45, № 2, P. 16–33. DOI: 10.15407/emodel.45.02.016
Pong, P. С. (2006), RTL hardware design using VHDL: coding for efficiency, portability, and scalability, Wiley-IEEE Press, 694 p. DOI: 10.1002/0471786411
Shkil A.S., Miroshnyk M., Kulak E., Filippenko I., Kucherenko D., Grebenyuk A. (2018), "Synchronizing sequences for verification of finite state machines", 9th International IEEE Conference Dependable Systems, Services and Technologies, DESSERT’2018, Ukraine, Kyiv May 24-27, P. 226–230. DOI: 10.1109/UkrMiCo47782.2019.9165509
Shkil А. S., Kruvulia G. F. (1981), "Automation of Boolean differences obtention" ["Avtomatizacija poluchenija bulevyh raznostej"], ACS and automation devices, Vol. 59, P. 73–78.
Hahanov V. I., Yemelianov I. V., Lubarskiy M. M., Chumachenko S. V., Litviniva Е. I., Bani A. T. (2017), "A qubit method for deductive fault analysis for logic circuits" ["Kubitnyj metod deduktivnogo analiza neispravnostej dlja logicheskih shem"], Electronic simulation, Vol. 39, № 6, P. 59–91.
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