Development of floating point operating devices

Authors

DOI:

https://doi.org/10.15587/2706-5448.2023.290127

Keywords:

floating-point multiplier, superscalar processor, associativity law, Baugh-Wooley algorithm, CISC-RISC

Abstract

The paper shows a well-known approach to the construction of cores in multi-core microprocessors, which is based on the application of a data flow graph-driven calculation model. The architecture of such kernels is based on the application of the reduced instruction set level data flow model proposed by Yale Patt. The object of research is a model of calculations based on data flow management in a multi-core microprocessor.

The results of the floating-point multiplier development that can be dynamically reconfigured to handle five different formats of floating-point operands and an approach to the construction of an operating device for addition-subtraction of a sequence of floating-point numbers are presented, for which the law of associativity is fulfilled without additional programming complications. On the basis of the developed circuit of the floating-point multiplier, it is possible to implement various variants of the high-speed multiplier with both fixed and floating points, which may find commercial application. By adding memory elements to each of the multiplier segments, it is possible to get options for building very fast pipeline multipliers. The multiplier scheme has a limitation: the exponent is not evaluated for denormalized operands, but the standard for floating-point arithmetic does not require that denormalized operands be handled. In such cases, the multiplier packs infinity as the result.

The implementation of an inter-core operating device of a floating-point adder-subtractor can be considered as a new approach to the practical solution of dynamic planning tasks when performing addition-subtraction operations within the framework of a multi-core microprocessor. The limitations of its implementation are related to the large amount of hardware costs required for implementation. To assess this complexity, an assessment of the value of the bits of its main blocks for various formats of representing floating-point numbers, in accordance with the floating-point standard, was carried out.

Author Biographies

Georgi Luсkij, National Technical University of Ukraine «Igor Sikorsky Kyiv Polytechnic Institute»

Doctor of Technical Science, Professor

Department of Computer Engineering

Oleksandr Dolholenko, National Technical University of Ukraine «Igor Sikorsky Kyiv Polytechnic Institute»

PhD, Associate Professor, Senior Researcher

Department of Informatics

References

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Development of floating point operating devices

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Published

2023-10-31

How to Cite

Luсkij G., & Dolholenko, O. (2023). Development of floating point operating devices. Technology Audit and Production Reserves, 5(2(73), 11–17. https://doi.org/10.15587/2706-5448.2023.290127

Issue

Vol. 5 No. 2(73) (2023): Information and control systems

Section

Information Technologies

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Copyright (c) 2023 Georgi Luсkij, Oleksandr Dolholenko

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