Estimation of the impact of a software update on indicators of reliability of a fault tollerant multiprocessor system

Authors

  • Богдан Юрійович Волочій Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine, Ukraine
  • Володимир-Мирон Володимирович Міськів Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine, Ukraine
  • Олександр Володимирович Муляк Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine, Ukraine
  • Леонід Діонісійович Озірковський Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine, Ukraine

DOI:

https://doi.org/10.15587/1729-4061.2013.14851

Keywords:

reliability of hardware/software systems, fault-tolerant hardware/software systems, fault-tolerant multiprocessor system

Abstract

This article outlines a Fault-Tolerant Multiprocessor System, designed for prolonged uninterrupted operation. During system operation software is updated with new versions, ensuring the increase of system reliability. The discussed model of the Fault-Tolerant Multiprocessor System is proposed to define reliability mesures. The designincludes two multiprocessor systems (main and reserve), processors with a joint sliding reserve, a control processor and system diagnostics. The model accounts for a software double update, as well as for automatic system reset after default caused by the hardware failures. The duration of faultless performance of the fault-tolerant multiprocessor system is calculated, and compared between two models: the proposed one, which takes into account the software update, and another well-known model, which does not include software updates.

Author Biographies

Богдан Юрійович Волочій, Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine

Doctor of Technical Sciences (DSc), Professor

Department of Theoretical Radio Engineering and Measuring

Володимир-Мирон Володимирович Міськів, Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine

Candidate of Technical Sciences (PhD), Associate Professor

Department of Electronic Eevices and Systems

Олександр Володимирович Муляк, Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine

PhD candidate

Department of Theoretical Radio Engineering and Measuring

Леонід Діонісійович Озірковський, Lviv Polytechnic National University Bandery Str., 12, Lviv, 79013, Ukraine

Candidate of Technical Sciences (PhD)

Department of Theoretical Radio Engineering and Measuring

References

  1. Mudry, P. A. CONFETTI: A reconfigurable hardware platform for prototyping cellular architectures. International Parallel and Distributed Processing Symposium [Текст] / Mudry, P. A., Vannel, F., Tempesti, G., Mange, D. – 2007. - P. 96–103.
  2. Viktorov, O. Reconfigurable Multiprocessor System Reliability Esimation [Текст] / Viktorov, O. // Asian Jounal of Information Technology. – 2007. - P. 958–960.
  3. Rajesh, S. Fault Tolerance in Multicore Processors With Reconfigurable Hardware Unit. [Текст] / Rajesh, S., Vinoth Kumar C., Srivatsan, R., Harini, S., Shanthi, A. // 15th international conference on high performance computing: Bangalore, INDIA. -2008. - P. 166–171.
  4. Amerijckx, C. A Low-Power Multiprocessor Architecture For Embedded Reconfigurable Systems [Текст] / Amerijckx, C., Legat, J.-D. // Power and Timing Modeling, Optimization and Simulation, International Workshop. – 2008. - P. 83–93.
  5. Реконфигурируемые мультиконвейерные вычислительные структуры [Текст] / И.А. Каляев, И.И. Левин, Е.А. Семерников, В.И. Шмойлов. – Ростов-на-Дону.: Издательство ЮНЦ РАН, 2008. – 393 c.
  6. Changyun, Zhu. Reliable multiprocessor system-on-chip synthesis [Текст] / Changyun Zhu, Gu, Z., Dick, R., Shang, L. // Proc. International Conference Hardware/Software Codesign and System Synthesis. – 2007. – P. 239–244.
  7. Kim, P. Gostelow. The design of a fault-tolerant, realtime, multi-core computer system [Текст] / Kim, P. Gostelow. // In Aerospace Conference, IEEE. -2011. - P. 1–8.
  8. Melson, N., James, D. (1983). Use of CYBER 203 and CYBER 205 computers for three-dimensional transonic flow calculations. National Aeronautics and Space Administration, Scientific and Technical Information Branch, 13 p.
  9. Белый, Ю. А. Модели отказов и оценка надежности мультидиверсных систем [Текст] / Ю. А. Белый // Радіоелектронні і комп’ютерні системи. – 2008. – №5 (32). – С. 62 – 66.
  10. Коротун, Т.М. Моделі і методи тестування програмних систем / Т.М. Коротун // Проблеми програмування. – 2007. – № 2. – С. 76 – 84.
  11. Волочій, Б. Ю. Технологія моделювання алгоритмів поведінки інформаційних систем / Б. Ю. Волочій. – Львів: Вид-во Національного університету “Львівська політехніка”, 2004. – 220 с.
  12. Романкевич, В.О. Про розрахунок надійності відмовостійких багатопроцесорних систем, підсистеми яких мають спільні процесори / В.О. Романкевич, А.П. Фесенюк // Радіоелектронні і комп’ютерні системи. – 2010. – №3 (44). – С. 62-67
  13. Волочій, Б. Ю. Оцінка показників надійності програмно-апаратної системи на основі мажоритарної структури з перезавантаженням програмного забезпечення / Б. Ю. Волочій, М. М. Змисний, О. В. Муляк. – Збірник тез доповідей ІХ науково-практичної конференції «Проблеми та перспективи розвитку економіки, підприємництва та комп'ютерних технологій в Україні». – Львів, 2013. – С. 503 - 507.
  14. Mudry, P.A., Vannel, F., Tempesti, G., Mange, D. (2007). A reconfigurable hardware platform for prototyping cellular architectures. International Parallel and Distributed Processing Symposium, 96–103.
  15. Viktorov, O. (2007). Reconfigurable Multiprocessor System Reliability Esimation. Asian Jounal of Information Technology, 958–960.
  16. Rajesh, S., Vinoth Kumar C., Srivatsan, R., Harini, S., Shanthi, A. (2008). Fault Tolerance in Multicore Processors With Reconfigurable Hardware Unit. 15th international conference on high performance computing: Bangalore, INDIA, 166–171.
  17. Amerijckx, C., Legat, J.-D. (2008). A Low-Power Multiprocessor Architecture For Embedded Reconfigurable Systems. Power and Timing Modeling, Optimization and Simulation, International Workshop, 83–93.
  18. Kaliaiev, I.A. (2008) Reconfigurable computing multiline structure Rostov-na-Donu, Publishing YUNC RAN, 393 p.
  19. Changyun Zhu, Gu, Z., Dick, R., Shang, L. (2007). Reliable multiprocessor system-on-chip synthesis. Proc. International Conference Hardware/Software Codesign and System Synthesis, 239–244.
  20. Kim P. Gostelow. (2011). The design of a fault-tolerant, realtime, multi-core computer system. In Aerospace Conference, IEEE, 1–8.
  21. Melson, N., James, D. (1983). Use of CYBER 203 and CYBER 205 computers for three-dimensional transonic flow calculations. National Aeronautics and Space Administration, Scientific and Technical Information Branch, 13 p.
  22. Belyi, Yu. A. (2008). Failure model and the assessment of the reliability of multidiversen systems. Radio-electronic and computer systems, №5 (32), 62-66.
  23. Korotun, Т. М. (2007) Models and methods for testing software systems. Programming problems, № 2, 76-84.
  24. Volochiy, B. Y. (2004) Technology of modeling algorithm the information systems. Lviv: Publishing NU "Lviv Polytechnic", 220 p.
  25. Romankevuch, V. O., Fesenyuk, A. P. (2010). About reliability calculation of fault-tolerant multiprocessor systems, which subsystems have common processors. Radio-electronic and computer systems, №3 (44), 62-67.
  26. Volochiy, B. Y., Zmysnyy, M. M., Mulyak, O. V. (2013). Reliability Estimation the software-hardware systems based on majoritarian structure with software restart Lviv - Collected Abstracts IX scientific conference "Problems and prospects of the economy, business and computer technology in Ukraine", 503 - 507.

Published

2013-06-19

How to Cite

Волочій, Б. Ю., Міськів, В.-М. В., Муляк, О. В., & Озірковський, Л. Д. (2013). Estimation of the impact of a software update on indicators of reliability of a fault tollerant multiprocessor system. Eastern-European Journal of Enterprise Technologies, 3(9(63), 55–59. https://doi.org/10.15587/1729-4061.2013.14851

Issue

Section

Information and controlling system