DOI: https://doi.org/10.15587/1729-4061.2019.168485

Optimal performance of 16-bit acyclic adders of binary codes

Mykhailo Solomko, Petro Tadeyev, Vitalii Nazaruk, Nataliia Khariv

Abstract


The conducted studies established the prospect for enhancing the performance of computing components, specifically, combinational 16-bit adders, based on the use of the principles of computation of digital signals of an acyclic model.

The application of an acyclic model for the synthesis of 16-bit parallel adders is designed for:

– the process of sequential (for lower bits) and parallel (for all other bits) computation of the sum and carry signals. Thanks to this approach, it becomes possible to reduce eventually the complexity of the hardware part without increasing the circuit depth;

– fixation (planning) of the adder circuit depth before its synthesis. This makes it possible to use the logical structure of transitive carry, which ensures the optimal adder circuit depth and does not increase its complexity.

Utilizing an acyclic model for the construction of 16-bit parallel adders is more beneficial in comparison with the analogs by the following factors:

– the lower cost development, since an acyclic model determines a simpler

structure of a 16-bit adder;

– application of the latest developed logical structures of transitive carry,

which makes it possible to decrease the delay of sum and carry signals, area, power consumption and to increase overall efficiency of 16-bit adders of binary codes.

Due to this, the possibility of obtaining optimal values of structure complexity and the depth of the adder circuit is ensured. In comparison with the analogs, it provides an increase in quality of indicator of 16-bit acyclic adders, such as power consumption, chip area by 15–27 %, depending on the chosen structure, and performance by 10–60 %.

There are some grounds to argue about the possibility of enhancing the performance of computing components, specifically, 16-bit adders of binary codes by using the principles of computation of digital signals of an acyclic model.

Keywords


optimal performance of acyclic adders; Ling Adder; Kogge-Stone Adder; Knowles Adder

References


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Solomko, M., Tadeyev, P., Zubyk, Y., Hladka, O. (2019). Reduction and optimal performance of acyclic adders of binary codes. Eastern-European Journal of Enterprise Technologies, 1 (4 (97)), 40–53. doi: https://doi.org/10.15587/1729-4061.2019.157150

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Michael Preetam Raj, P., Sandeep, B., Sai Mallik Reddy, D., Ramanjaneyulu, P., Sai Pravallika, S. (2016). Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder. Indian Journal of Science and Technology, 9 (13). doi: https://doi.org/10.17485/ijst/2016/v9i13/87911

Shanil Mohamed, N., Siby, T. Y. (2014). 16-bit velocious fault lenient parallel prefix adder. 2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE). doi: https://doi.org/10.1109/icecce.2014.7086612

Poornima, N., Bhaaskaran, V. S. K. (2015). Area Efficient Hybrid Parallel Prefix Adders. Procedia Materials Science, 10, 371–380. doi: https://doi.org/10.1016/j.mspro.2015.06.069

Payal, R., Goel, M., Manglik, P. (2015). Design and Implementation of Parallel Prefix Adder for Improving the Performance of Carry Lookahead Adder. International Journal of Engineering Research & Technology, 4 (12), 566–571. doi: https://doi.org/10.17577/ijertv4is120608

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Class ECE6332 Fall 12 Group-Fault-Tolerant Reconfigurable PPA. Available at: http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ClassECE6332Fall12Group-Fault-Tolerant_Reconfigurable_PPA

Two-Operand Addition. Available at: https://pubweb.eng.utah.edu/~cs5830/Slides/addersx6.pdf

Knowles, S. (1999). A family of adders. Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336). doi: https://doi.org/10.1109/arith.1999.762825

Sklansky, J. (1960). Conditional-Sum Addition Logic. IEEE Transactions on Electronic Computers, EC-9 (2), 226–231. doi: https://doi.org/10.1109/tec.1960.5219822

Han, T., Carlson, D. A. (1987). Fast area-efficient VLSI adders. 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH). doi: https://doi.org/10.1109/arith.1987.6158699

Ladner, R. E., Fischer, M. J. (1980). Parallel Prefix Computation. Journal of the ACM, 27 (4), 831–838. doi: https://doi.org/10.1145/322217.322232

Brent, R., Kung, H. T. (1982). A Regular Layout for Parallel Adders. IEEE Transactions on Computers, C-31 (3), 260–264. doi: https://doi.org/10.1109/tc.1982.1675982


GOST Style Citations


Solomko M. Optimization of the acyclic adders of binary codes // Technology audit and production reserves. 2018. Vol. 3, Issue 2 (41). P. 55–65. doi: https://doi.org/10.15587/2312-8372.2018.133694 

Reduction and optimal performance of acyclic adders of binary codes / Solomko M., Tadeyev P., Zubyk Y., Hladka O. // Eastern-European Journal of Enterprise Technologies. 2019. Vol. 1, Issue 4 (97). P. 40–53. doi: https://doi.org/10.15587/1729-4061.2019.157150 

Baba Fariddin S., Vargil Vijay E. Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder // International Journal of Computer Applications. 2013. Vol. 79, Issue 16. P. 11–14. doi: https://doi.org/10.5120/13943-1784 

Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder / Michael Preetam Raj P., Sandeep B., Sai Mallik Reddy D., Ramanjaneyulu P., Sai Pravallika S. // Indian Journal of Science and Technology. 2016. Vol. 9, Issue 13. doi: https://doi.org/10.17485/ijst/2016/v9i13/87911 

Shanil Mohamed N., Siby T. Y. 16-bit velocious fault lenient parallel prefix adder // 2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE). 2014. doi: https://doi.org/10.1109/icecce.2014.7086612 

Poornima N., Bhaaskaran V. S. K. Area Efficient Hybrid Parallel Prefix Adders // Procedia Materials Science. 2015. Vol. 10. P. 371–380. doi: https://doi.org/10.1016/j.mspro.2015.06.069 

Payal R., Goel M., Manglik P. Design and Implementation of Parallel Prefix Adder for Improving the Performance of Carry Lookahead Adder // International Journal of Engineering Research & Technology. 2015. Vol. 4, Issue 12. P. 566–571. doi: https://doi.org/10.17577/ijertv4is120608 

Simulation study of brent kung adder using cadence tool / Vamshi Krishna T., Niveditha S., Mamatha G. N., Sunil M. P. // International Journal of Advance Research, Ideas and Innovations in Technology. 2018. Vol. 4, Issue 3. P. 564–573. URL: https://www.ijariit.com/manuscripts/v4i3/V4I3-1383.pdf

Design of 16-Bit Adder Structures-Performance Comparison / Padma Balaji R. D., Tarun P., Yeswanth Kumar E., Anita Angeline A. // International Journal of Pure and Applied Mathematics. 2018. Vol. 118, Issue 24. URL: https://acadpubl.eu/hub/2018-118-24/3/492.pdf

Kaneko M. A Novel Framework for Procedural Construction of Parallel Prefix Adders // 2019 IEEE International Symposium on Circuits and Systems (ISCAS). 2019. doi: https://doi.org/10.1109/iscas.2019.8702117 

Sumator z pryskorenym perenosom: Pat. No. 117572U UA. MPK G 06 F 7/38 (2006.01) / Krulikovskyi B. B., Vozna N. Ya., Hryha V. M., Nykolaichuk Ya. M., Davletova A. Ya. No. u201701336; declareted: 13.02.2017; published: 26.06.2017, Bul. No. 12.

Gedam S. K., Zode P. P. Parallel prefix Han-Carlson adder // International Journal of Research in Engineering and Applied Sciences. 2014. Vol. 02, Issue 02. P. 81–84. URL: http://www.mgijournal.com/pdf_new/Electronics/Swapna%20Gedam-1.pdf

Zeydel B. R., Baran D., Oklobdzija V. G. Energy-Efficient Design Methodologies: High-Performance VLSI Adders // IEEE Journal of Solid-State Circuits. 2010. Vol. 45, Issue 6. P. 1220–1233. doi: https://doi.org/10.1109/jssc.2010.2048730 

Govindarajulu S., Vijaya Durga Royal T. Design of Energy-Efficient and High-Performance VLSI Adders // International Journal of Engineering Research. 2014. Vol. 3. P. 55–59. URL: https://pdfs.semanticscholar.org/a54c/5727cdc2be7830ea734f15eb1ba9ecfc2110.pdf

Pinto R., Shama K. Efficient shift-add multiplier design using parallel prefix adder // International Journal of Control Theory and Applications. 2016. Vol. 9, Issue 39. P. 45–53.

Kogge P. M., Stone H. S. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations // IEEE Transactions on Computers. 1973. Vol. C-22, Issue 8. P. 786–793. doi: https://doi.org/10.1109/tc.1973.5009159

Class ECE6332 Fall 12 Group-Fault-Tolerant Reconfigurable PPA. URL: http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ClassECE6332Fall12Group-Fault-Tolerant_Reconfigurable_PPA

Two-Operand Addition. URL: https://pubweb.eng.utah.edu/~cs5830/Slides/addersx6.pdf

Knowles S. A family of adders // Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336). 1999. doi: https://doi.org/10.1109/arith.1999.762825

Sklansky J. Conditional-Sum Addition Logic // IEEE Transactions on Electronic Computers. 1960. Vol. EC-9, Issue 2. P. 226–231. doi: https://doi.org/10.1109/tec.1960.5219822

Han T., Carlson D. A. Fast area-efficient VLSI adders // 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH). 1987. doi: https://doi.org/10.1109/arith.1987.6158699

Ladner R. E., Fischer M. J. Parallel Prefix Computation // Journal of the ACM. 1980. Vol. 27, Issue 4. P. 831–838. doi: https://doi.org/10.1145/322217.322232

Brent R., Kung H. T. A Regular Layout for Parallel Adders // IEEE Transactions on Computers. 1982. Vol. C-31, Issue 3. P. 260–264. doi: https://doi.org/10.1109/tc.1982.1675982







Copyright (c) 2019 Mykhailo Solomko, Petro Tadeyev, Vitalii Nazaruk, Nataliia Khariv

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ISSN (print) 1729-3774, ISSN (on-line) 1729-4061