Optimal performance of 16-bit acyclic adders of binary codes

Authors

DOI:

https://doi.org/10.15587/1729-4061.2019.168485

Keywords:

optimal performance of acyclic adders, Ling Adder, Kogge-Stone Adder, Knowles Adder

Abstract

The conducted studies established the prospect for enhancing the performance of computing components, specifically, combinational 16-bit adders, based on the use of the principles of computation of digital signals of an acyclic model.

The application of an acyclic model for the synthesis of 16-bit parallel adders is designed for:

– the process of sequential (for lower bits) and parallel (for all other bits) computation of the sum and carry signals. Thanks to this approach, it becomes possible to reduce eventually the complexity of the hardware part without increasing the circuit depth;

– fixation (planning) of the adder circuit depth before its synthesis. This makes it possible to use the logical structure of transitive carry, which ensures the optimal adder circuit depth and does not increase its complexity.

Utilizing an acyclic model for the construction of 16-bit parallel adders is more beneficial in comparison with the analogs by the following factors:

– the lower cost development, since an acyclic model determines a simpler

structure of a 16-bit adder;

– application of the latest developed logical structures of transitive carry,

which makes it possible to decrease the delay of sum and carry signals, area, power consumption and to increase overall efficiency of 16-bit adders of binary codes.

Due to this, the possibility of obtaining optimal values of structure complexity and the depth of the adder circuit is ensured. In comparison with the analogs, it provides an increase in quality of indicator of 16-bit acyclic adders, such as power consumption, chip area by 15–27 %, depending on the chosen structure, and performance by 10–60 %.

There are some grounds to argue about the possibility of enhancing the performance of computing components, specifically, 16-bit adders of binary codes by using the principles of computation of digital signals of an acyclic model.

Author Biographies

Mykhailo Solomko, National University of Water and Environmental Engineering Soborna str., 11, Rivne, Ukraine, 33028

PhD, Associate Professor

Department of Computer Engineering

Petro Tadeyev, National University of Water and Environmental Engineering Soborna str., 11, Rivne, Ukraine, 33028

PhD, Doctor of Pedagogical Sciences, Professor

Department of Higher Mathematics

Vitalii Nazaruk, National University of Water and Environmental Engineering Soborna str., 11, Rivne, Ukraine, 33028

PhD

Department of Computer Engineering

Nataliia Khariv, National University of Water and Environmental Engineering Soborna str., 11, Rivne, Ukraine, 33028

Senior Lecturer

Department of Applied Mathematics

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Published

2019-05-27

How to Cite

Solomko, M., Tadeyev, P., Nazaruk, V., & Khariv, N. (2019). Optimal performance of 16-bit acyclic adders of binary codes. Eastern-European Journal of Enterprise Technologies, 3(4 (99), 21–36. https://doi.org/10.15587/1729-4061.2019.168485

Issue

Vol. 3 No. 4 (99) (2019): Mathematics and Cybernetics - applied aspects

Section

Mathematics and Cybernetics - applied aspects

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Copyright (c) 2019 Mykhailo Solomko, Petro Tadeyev, Vitalii Nazaruk, Nataliia Khariv

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