Genetic algorithm for constructing functional tests of arithmetic logic units
DOI:
https://doi.org/10.15587/1729-4061.2014.22407Keywords:
digital device, system-on-chip, built-in self-test, functional test, genetic algorithmAbstract
A genetic algorithm for constructing functional-level test sequences for built-in self-test schemes of arithmetic logic units of modern systems-on-chip is proposed in the paper. The idea of the method lies in the automated construction of functional tests, which are arithmetic operands, allowing maximum coverage of the selected type of damages of the structural level, at which test is considered as a binary set. In fact, providing input sets and checking reactions are performed directly by the arithmetic logic unit. Since the task concerns two-level representation of the digital device with an appropriate representation of input tests, two types of genetic operations, namely binary and arithmetic are used in the method. Inversion of input/output lines of arithmetic logic unit is selected as a functional level coverage metrics.Approbation of the proposed algorithm is performed for arithmetical division. It is experimentally shown that the functional test with the length of seven sets allows covering about 90% of constant structural-level damages. The test compression level with respect to the structural level is more than 100 times.фReferences
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