Synthesis of recursive-type neural elements with parallel vertical-group data processing
DOI:
https://doi.org/10.15587/1729-4061.2025.329139Keywords:
model of a neural element, real-time calculations, hardware implementation of a neural elementAbstract
The object of this study is the processes of parallel vertical-group data processing and minimization of equipment costs, which enable the synthesis of real-time recursive neural elements with high efficiency of equipment use. A model of a recursive-type neural element has been built, which, through the use of a parallel vertical-group method for calculating the scalar product and the ability to choose the number of bits in the group for the formation of partial products, coordinates the time of receipt of weights and input data with the time of calculating the result at the output of the neural element. This approach provides a hardware implementation of the neural element with minimal use of equipment.
The basic structure of the neural element has been designed, which, through the use of hardware mapping of the constructed graph model, regularity, and modularity of the structure, provides the synthesis of hardware for a specific application. The application of pipelines and spatial parallelism of data processing, as well as the organization of the process of calculating the scalar product, as the performance of a single operation, enables the implementation of a neural element for real-time operation.
Analytical expressions have been built to estimate the parameters of a neural element depending on the bit depth of operands, the number of data inputs, and the number of bits in the group. A method for synthesizing a recursive-type neural element has been devised, which, due to the use of the basic structure, enables mechanisms for matching the time of receipt of weight coefficients and input data with the time of calculating the output, thus ensuring its implementation for specific applications. Considering ways to minimize equipment costs ensures the construction of a neural element with minimal hardware costs.
The synthesized neural element for a data depth of 16 bits with an increase in the number of bits that are simultaneously processed in a group, from 2 to 8, provides a decrease in the processing time by 2.8 times with a reduction in the efficiency of using the equipment of the neural element by no more than 1.6 times
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Copyright (c) 2025 Ivan Tsmots, Vasyl Teslyuk, Yurii Opotyak, Taras Mamchur, Oleksandr Oliinyk

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